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p reliminary w89c926 pentic+ pcmcia ethernet network twisted pair interface controller publication release date: january 1996 - 1 - revision a1 general description the w89c926 pentic+ is a cmos device designed for easy implementation of pcmcia r2.1 compatible csma/cd local area networks. the w89c926 combines a w89c902 serial lan coprocessor for twisted-pair (slct) with a pcmcia bus interface (pbi) , thus integrating into a single chip all the registers and logic necessary to connect the slct to buffer srams, flash memories (or an eeprom), and the pcmcia system bus. the pcmcia bus interface (pbi) is designed to provide a switchless setting architecture that allows the card setting to be configured by software. it implements a full set of pcmcia registers for pcmcia r2.1 compatibility and a set of configuration registers for switchless card setting. the card can be configured quickly and easily by modi fying the contents of the configuration registers. the pentic+ can run with shared memory mode and ne2000 tm i/o mode drivers on a 16-bit bus interface. no extra effort is needed to ensure software compatibility. the pentic+ provides a flexible flash memory (up to 128 kb)/eeprom (up to 512 bytes) architecture for pcmcia nonvolatile storage and an id/configuration auto-load architecture for power-on initialization. vendors can store the ethernet id, configuration, and cis in the flash memory or eeprom. the pentic+ will auto-load necessary information when power is switched on. features runs with ne2000 tm or shared memory drivers supports up to 128 kb flash memory (8k/112k for attribute/common memory) or 512 bytes eeprom (for attribute memory only) for nonvolatile memory uses one 16 kb sram or one 32 kb sram (if eeprom is used) for 16 kb ethernet ring buffer auto-load algorithm provided for power-on initialization supports necessary pcmcia registers configuration registers allow switchless card setting utp/bnc auto media-switching function provided drives necessary leds for network status display single 5v power supply with low power consumption 100-pin thin package (tqfp) fits into pcmcia type ii profile ethernet a is a registered trademark of the xerox corporation. ne2000 tm is a trademark of novell, inc.
w89c926 pentic+ - 2 - pin configuration 32 31 1 2 3 4 5 6 7 8 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 2 9 2 3 2 4 2 5 2 6 2 7 2 8 3 0 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 5 1 5 2 5 3 5 4 5 5 5 6 5 7 5 8 5 9 6 0 6 1 6 2 6 3 6 4 6 5 6 6 6 7 6 8 6 9 7 0 7 1 7 2 7 3 7 4 7 5 7 6 7 7 7 8 7 9 8 0 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 . h d 1 0 h d 2 v c c h d 9 g n d h d 1 h d 0 h a 0 h d 8 h a 1 / r e g h a 2 / i n p a c k d g n d h a 3 d v c c / w a i t h a 4 h a 5 h a 6 r e s e t h a 1 2 h a 1 5 h a 7 / i r e q h a 1 6 h a 1 4 / w e h a 1 3 h a 8 iowr ha9 iord ha11 oe ce2 ha10 hd15 ce1 hd14 hd7 hd13 gnd hd6 hd12 hd5 hd11 hd4 hd3 t h i n r x i + r x i - g n d x 1 x 2 / g d l n k / a c t l e d m s a 1 5 c d + c d - r x + t x + t x - r x - t x o + t x o - a g n d m s a 1 6 m s d 3 m s d 4 m s d 5 m s d 6 m s d 7 e e c s , / f c s / r c s m s a 1 0 / m s r d m s a 1 1 a v c c v cc msa8 msa13 mswr msd0 msa1 msa3 msa9 gnd msd2 msd1 msa0 msa2 msa4 msa5 msa6 msa7 msa12 msa14 ios16 v cc
w89c926 pentic+ publication release date: january 1996 - 3 - revision a1 pin description name number type description pcmcia bus interface ha0-2 ha3, 4 ha5-7 ha8-10 ha11-13 ha14-16 9, 10, 12 15, 18 20-22 30, 32, 37 34, 23,29 28, 24, 25 i/ttl host address bus: host address lines used to decode access to the card's memory and i/o spaces. hd0-2 hd3-5 hd6-8 hd9-11 hd12-15 8, 6, 2 50, 49, 47 44, 41, 7 4, 1, 48 46, 42, 40, 38 io/3sh host data bus: bidirectional host data bus. ireq 26 o/ttl interrupt request: ireq is asserted by the pentic+ to request host service. during auto-loading, which is caused by a h/w reset, ireq will assert low until auto-loading is complete. this signaling is used as rdy/-bsy of memory only interface during initialization, according to pcmcia r2.1. iord 33 i/ttl i/o read: iord is asserted by the system to read data from the card's i/o space. it has an internal 100k ohm pull-high resistor. iowr 31 i/ttl i/o write: iowr is asserted by the system to write data to the card's i/o space. it has an internal 100k ohm pull-high resistor. we 27 i/ttl write enable: the we input is asserted by the system to strobe memory write data into the card memory. it has an internal 100k ohm pull-high resistor.
w89c926 pentic+ - 4 - pin description, continued name number type description oe 35 i/ttl output enable: the oe line is asserted by the system to obtain memory read data from the card memory. it has an internal 100k ohm pull-high resistor. ce 1 , 2 39, 36 i/ttl card enable: ce 1 , 2 are asserted by the system for data bus width control as shown below. these pins have an internal 100k ohm pull-high resistor. ce2 ce hd15-hd8 hd7-hd0 0 0 1 1 0 1 0 1 valid valid high-z high-z valid high-z valid high-z reg 11 i/ttl register & i/o selection: reg is asserted by the system to access attribute memory or i/o space. it remains high inactive for common memory ac cesses. it has an internal 100k ohm pull-high resistor. iois 16 100 o/ttl 16-bit i/o access: asserted by the pentic+ to inform the system that current op eration is a 16-bit i/o access. inpack 13 o/ttl input acknowledge: asserted by the pentic+ when it has been selected and can respond to an i/o read cycle. wait 17 o/ttl wait state: asserted by the pentic+ to insert wait states into current memory or i/o access cycles. reset 19 i/ttl card reset: a reset pulse will initiate the pentic+'s initialization procedure, including auto-id/configuration loading, register initialization, and state machine initialization. the pulse width should be at least 500 ns to be recognized as a valid reset. this pin has an internal 100k ohm pull-up resistor.
w89c926 pentic+ publication release date: january 1996 - 5 - revision a1 pin description, continued name number type description memory support interface msa0-7 msa8-10 msa11-13 msa14-16 90-97 82, 81, 78 80, 98, 84 99, 69, 70 o/ttl memory support address: latched address used to decode accesses to the on- board memory. msd0-2 msd3-7 89-87 71-75 io/3sh i/o/3sh memory support data bus: bidirectional on-board memory data bus. eeprom interface: during the eeprom auto-load or read/write sequence, msd0 is used as a serial data input/output from/to eeprom, msd1 outputs eeprom commands to eeprom, and msd2 sends a clock with a period of 1.2 microseconds. this function is available only when eecs/ fcs is low during h/w reset. rcs 77 o/ttl sram chip select: rcs is asserted by the pentic+ for sram chip enable during buffer memory access. eecs/ fcs 76 o/3sh i/3sh nonvolatile memory chip select: eecs/ fcs is asserted by the pentic+ for chip en able during nonvolatile memory access. it is active low for flash memory enable and active high for eeprom chip enable. nonvolatile memory detection: during h/w reset, the pentic+ will determine the existing nonvolatile memory type by sampling the voltage level on this pin. if this pin is externally pulled high with a 470k ohm resistor, the pentic+ will determine that the memory is a flash memory; if the pin is pulled low with a 470k ohm resistor, it will determine that the memory is an eeprom. msrd 79 o/ttl memory support read: msrd is asserted by the pentic+ to strobe read data from the on-board memory. both sram and flash memory use msrd as the read command strobe.
w89c926 pentic+ - 6 - pin description, continued name number type description mswr 86 o/ttl memory support write: mswr is asserted by the pentic+ to strobe write data into the on-board memory. both sram and flash memory use mswr as the write command strobe. network interface txo+, - 60, 59 o/dif twisted pair transmit outputs: utp differential output pair. a 1.21 k w precision resistor should be shunted across these pins for signal pre- equalization. rxi+, - 58, 57 i/dif twisted pair receive inputs: these inputs are fed into a differential amplifier which passes valid data to the lce core. a 100 w precision resistor should be shunted across these pins for impedance matching. tx+, - 64, 63 o/dif aui transmit outputs: differential transmit outputs. these pins should be con- nected to 270 ohm external pull-down resistors. rx+, - 66, 65 i/dif aui receive inputs: differential receive input pair from aui interface. cd+, - 68, 67 i/dif aui collision inputs: differential collision input pair from aui interface. x1 55 i/xtal crystal input: master 20 mhz clock input. x2 54 o/xtal crystal feedback output: this pin should be connected to the crystal when a crystal is used and should be left unconnected when an oscillator is used. thin 51 o/ttl thin cable select: this pin is high when the pentic+ is configured for thin cable media. it can be used as a switch to dc-dc con- verter for network media selection. actled 52 o/ttl activity: this output asserts low for approximately 50 ms whenever the pentic+ transmits or receives data without collisions. this output can also be controlled by the power-down state machine; refer to the descriptions of the cor and cfa registers for more details.
w89c926 pentic+ publication release date: january 1996 - 7 - revision a1 pin description, continued name number type description gdlnk 53 o/ttl goodlink: this output asserts low if the pentic+ is in tpi mode, link checking is enabled, and the link integrity is good or if link checking is disabled; otherwise, is not asserted. this output can also be controlled by power down state machine; refer to the description of the cor and cfa registers for more details. power pins av cc 61 analog power supply pins: these pins supply +5v to the pentic+'s analog circuitry for the network interface. analog layout rules and decoupling methods must be applied between this pin and agnd. agnd 62 analog ground pins: these pins are the ground to the analog circuitry. v cc 3, 16, 45, 83 digital power supply pins: these pins supply +5v to the pentic+'s digital circuitry. gnd 5, 14, 43, 56, 85 digital ground pins: these pins are the ground to the digital circuitry. note: i: input pin; o: output pin; io: bidirectional input/output pin; ttl: ttl level buffer stage; odh: open drain buffer stage; mos: mos level buffer stage; 3sh: tri-state buffer stage; dif: differential buffer stage, xtal: crystal.
w89c926 pentic+ - 8 - block diagram ha0-16 hd0-15 pcmcia slot pcmcia bus interface logic and drivers interrupt control flash memory control buffer memory control config. registers & control local bus arbiter id registers local bus eeprom control w89c902 core
w89c926 pentic+ publication release date: january 1996 - 9 - revision a1 system diagram w89c926 w89c92 optional tp/if leds osc/xtal pcmcia slot msd0-7 3 msa0-16 ha0-16 15 hd0-15 eeprom 93c56/66 (eecs/fcs pull low) flash 128kb x 1 (eecs/fcs pull high) sram or 32kb x 1 16 kb x 1 (eecs/fcs pull low) two combinations may be used for the hardware structure: combination 1: eecs/fcs pull high/128 kb x 1 flash memory/16 kb x 1 sram combination 2: eecs/fcs pull low/256 or 512b eeprom/32 kb x 1 sram functional description address mapping eeprom mapping eeprom address high byte low byte 00h - word count 01h cfb cfa 02h id-1 id-0 03h id-3 id-2 04h id-5 id-4 05h check sum board type (05h) 06h-08h - - 09h 57h 57h 0ah-nh cis cis (n+1) h-ffh - - notes: 1. the fifth (05h) word is used for shared memory mode and the ninth (09h) word is used for ne2000 mode. 2. word count = nh (n should be set as a non zero value, a zero value will cause an unpredicted error).
w89c926 pentic+ - 10 - attribute memory mapping eecs/fcs pull high (flash memory) attribute memory offset (ha0-16) type contents 00000h 00f9eh flash cis 00fa0h flash id-0 00fa2h flash id-1 00fa4h flash id-2 00fa6h flash id-3 00fa8h flash id-4 00faah flash id-5 00fach flash board type (05h) 00faeh flash check sum 00fb0h flash - 00fb2h flash - 00fb4h flash - 00fb6h flash - 00fb8h flash - 00fbah flash - 00fbch flash 57h 00fbeh flash 57h 00fc0h flash cfa 00fc2h flash cfb - - - 00fd0h register cor 00fd2h register ccsr 00fd4h register - 00fd6h register scr - register reserved (see note) 00ff0h register cfa 00ff2h register cfb 00ff4h register sr 00ff6h 00ffeh register reserved 01000h 03ffeh flash cis
w89c926 pentic+ publication release date: january 1996 - 11 - revision a1 eecs/fcs pull low (eeprom) attribute memory offset (ha0-16) type contents 00000h 003d6h memory (sram) cis - unsued - 00fd0h register cor 00fd2h register ccsr 00fd4h register - 00fd6h register scr - register reserved (see note) 00ff0h register cfa 00ff2h register cfb 00ff4h register sr 00ff6h 00ffeh register reserved 01000h 03ffeh unused - notes: 1.the reserved register space in the attribute space is left for future extension. users should not place their application in this area. 2. when eecs/ fcs is pulled high, address 00fa0h to 00ffeh is used for ethernet id, configuration, and registers. vendors should not put cis in this region. 3. when eecs/ fcs is pulled low, address 00000h to 003d6h is read-only. the pentic+ will ignore write accesses to this area. ne2000 mode mapping i/o mapping system i/o offset (ha0-4) name operation 00h 0fh lce core registers register read/write 10h 17h remote dma port remote dma read/write 18h 1fh reset port software reset notes: 1. the pentic+ decodes only ha0-4 for i/o access, so the iobase address is left for the host adapter and the socket service to determine. 2. to issue a s/w reset, simply issue an i/o read to the reset port. the pentic+ will assert a 600 ns internal reset pulse to reset the core state machine. if the host tries to access the p entic+, wait will be asserted low until the reset is completed.
w89c926 pentic+ - 12 - buffer memory mapping nic core memory map ne2000 compatible 0000h 001fh id registers 0020h 00ffh aliased 0100h 3fffh id registers 4000h 7fffh buffer sram (16k 8) 8000h bfffh aliased id registers c000h ffffh aliased buffer sram nonvolatile memory mapping f/ ee = 1 (flash memory used) system offset (ha0-16) memory type name 00000h 03fffh attribute/ flash cis/id/pcmcia register (8k 8) 04000h 1ffffh common/ flash (112k 8) f/ ee = 0 (eeprom used) system offset (ha0-16) memory type name 00000h 003d6h attribute/ (note) cis (492 8) notes: 1. this attribute memory is an image from eeprom. it is actually resident in upper half of the sram after power-on auto- loading. 2. refer to "attribute memory mapping" for detailed locations. 3. the pentic+ decodes ha0-16 for memory access. the (common or attribute) membase addresses are left for the host adapter and the socket service to determine.
w89c926 pentic+ publication release date: january 1996 - 13 - revision a1 shared memory mode mapping i/o mapping system i/o offset (ha0-4) name operation 00h mma i/o write 01h word/-byte i/o read 05h mmb i/o write 08h 0fh id registers i/o read 10h 1fh lce core registers register read/write notes: 1. the pentic+ decodes only ha0-4 for i/o access, so the iobase address is left for the host adapter and the socket service to determine. 2. mma and mmb are used for shared memory mapping control. since the pentic+ decodes only msa = 0000h to 03fffh for shared memory that is, the shared memory base address for the pentic+ is 00000h, mmb and bit 0 to 5 of mma should be set to 0. 3. since the pentic+ supports 16-bit mode only, the word/-byte will be read as 01h. buffer memory mapping system offset (ha0-16) memory type shared memory mode 00000h 03fffh common/sram buffer sram (16k 8) 04000h 07fffh common/(note) unused notes: 1. this region is occupied by flash memory. 2. the pentic+ decodes ha0-16 for memory access. the (common or attribute) membase addresses are left for the host adapter and the socket service to determine. nonvolatile memory mapping f/ ee = 1 (flash memory used) system offset (ha0-16) memory type name 00000h 03fffh attribute/ flash cis/id/pcmcia register (8k 8) 04000h 1ffffh common/ flash (112k 8)
w89c926 pentic+ - 14 - f/ ee = 0 (eeprom used) system offset (ha0-16) memory type name 00000h 003d6h attribute/ (note) cis (492x 8) notes: 1. this attribute memory is an image from eeprom. it is physically resident in upper half of the sram after power-on auto- loading. 2. refer to "attribute memory mapping" for detailed locations. 3. the pentic+ decodes ha0-16 for memory access. the (common or attribute) membase addresses are left for the host adapter and the socket service to determine. register file the w89c926 pentic+ has four register sets: the core register set, the pcmcia configuration register set, the lan configuration register set, and the special control register set. the core register set is the same as that in the w89c90 and will not be discussed here. the other three register sets are described below. pcmcia configuration register set the pentic+ provides three pcmcia configuration registers needed to ensure compatibility with various operating systems. cor (configuration option register) access address: ambase + 00fd0h access type: attribute memory read/write bit symbol description 0-5 idx0-5 configuration index these six bits are used to indicate entry of the card configuration table located in the cis (card information structure; refer to pcmcia r2.1). these bits are 0 at power-on. 6 - reserved, must be 1 (level mode interrupt) when read. 7 sreset s/w reset a software reset is issued when a 1 is written to this bit. this is the same as a h/w reset except that this bit and the necessary information (cfa, cfb, cis, and ethernet id) are not cleared, and the auto-load procedure is not performed. returning a 0 to this bit will leave the pentic+ in a post-reset state the same as that following a hardware reset. the value of this bit at power-on is 0.
w89c926 pentic+ publication release date: january 1996 - 15 - revision a1 ccsr (card configuration and status register) access address: ambase + 00fd2h access type: attribute memory read/write bit symbol description 0 - reserved, must be 0. 1 intr interrupt status this bit indicates the internal status of an interrupt request. it remains high until the condition that caused the interrupt request has been serviced. this bit is 0 at power-on. 2-7 - reserved, must be 0s. scr (socket and copy register) the scr is used to enable the pentic+ to distinguish between similar cards installed in the same system. access address: ambase + 00fd6h access type: attribute memory read/write bit symbol description 0-3 socnum socket number set these bits to indicate to the pentic+ that it is located in the n'th socket. the first socket is numbered 0. this permits any cards designed to do so to share a common set of io ports while remaining uniquely identifiable. these bits are 0 at power-on. 4-6 copnum copy number set these bits to indicate to the pentic+ that it is the n'th copy of another card installed in the system that is configured identically. the first identical card should be assigned a value of 0 as its copy number. this permits any cards designed to do so to share a common set of i/o ports while remaining uniquely identifiable and consecutively ordered. these bits are 0s at power-on. 7 - reserved, must be 0. lan configuration register set these two registers are used for lan configuration control. cfa (configuration register a) this register is used to select the pentic+'s operating mode and led control. access address: ambase + 00ff0h access type: attribute memory read/write
w89c926 pentic+ - 16 - bit symbol description 0 m/-io share memory/io mode select the pentic+ will operate in shared memory mode if this bit is high; otherwise, it will be in i/o mode. 1-5 - reserved, must be 0s. 6 f/ ee flash or eeprom select. this bit directly reflects the sampled value on pin eecs/ fcs during a h/w reset. this bit will be high or low if eecs/ fcs is pulled high or low. this bit is read-only. 7 led led disable. setting this bit high disables the led indicators in order to save power. cfb (configuration register b) access address: ambase + 00ff2h access type: attribute memory read/write bit symbol description 0-1 phy01 physical media select these two bits determine to which type of medium the pentic+ is attached. the thin pin will output low in 10base5 mode and high in 10base2 mode, according to phy0,1. this can be used to control the dc-dc con verter for electrical isolation. phy1 attached medium type tpi (10base-t compatible squelch level) thin ethernet (10base2) thick ethernet (10base5) tpi (reduced squelch level) phy0 0 0 0 1 1 0 1 1 the pentic+ also provides a utp/bnc auto media-switching function. the physical interface will jump from utp to bnc when the pentic+ is configured at utp, the link checking is enabled, and the utp path is broken. it will jump back immediately if the utp path has been reconnected. when the physical interface is not configured at tpi or the link checking is disabled, the auto media-switching function will be disabled.
w89c926 pentic+ publication release date: january 1996 - 17 - revision a1 cfb (configuration register b), continued bit symbol description 2 lnken link enable writing a "1" to this bit will disable the link pulse generation, auto media- switching function, and link integrity check function. writing a "0" to this bit will enable these functions. 3 lnksts link status this bit indicates the present link status. it is high if the pentic+ is in tpi mode, the link checking is en abled, and the link integrity is good or if the link checking is disabled; other wise, it is low. 4 io16con iois16 timing control. if this bit is set high, the iois16 signal will decode ce1,2 ; otherwise, iois16 is decoded according to ha and reg (default). 5 fwen flash write enable. the default setting for the flash memory is write-protected. if fwen = 1, the pentic+ allows the flash to be written to. the write command and chip select signal is prohibited if fwen = 0. 6 sramsel sram speed select. if sramsel = 1, the sram-15 is selected. otherwise, sram-70 is used. the default is sram-70. 7 - reserved. special control register set these registers are used for special checking or eeprom access control. signature register (sr) a signature register is used for identification so that the software driver can easily distinguish between different chips. the content can be read out in toggled order as follows: access address: ambase + 00ff4h access type: attribute memory read msb lsb (2n)th time: 10001000 where n = 1, 2, ... (after h/w reset) (2n-1)th time: 00000000 eeprom access register (eear) this register is located on page 3 and is used for eeprom read/write access control. it is inhibited when eecs/ fcs is pulled high. access address: iobase + 02h access type: i/o read/write
w89c926 pentic+ - 18 - bit symbol description 0-5 - reserved. must be 0s. 6 ew/ er eeprom write/read select. this bit selects the eeprom read/write sequence. if ew/ er = 1, the write sequence is selected. if ew/ er = 0, the read sequence is selected. 7 eos eeprom operation select. this bit enables the eeprom read/write sequence. if eos = 1, the eeprom read/write sequence will be started. eos is reset if the read/write sequence is finished or aborted. eeprom address/data register (adr) this register is located on page 3 and is used for eeprom address or data transfer during eeprom access. access address: iobase + 04h access type: i/o read/write power-on initialization and auto-loading process when powered on, the system should reset the card first, as required by the pcmcia specifications. the reset signal will trigger a number of internal operations: first, the pentic+ monitors the eecs/ fcs pin to determined where the configurations are stored. if this pin is pulled high, the configurations are stored in the flash memory; if it is pulled low, they are stored in an eeprom. then, within 10ms after the reset pulse is negated, the pentic+ will automatically load the configurations, id, and cis data into the lan configuration registers and the upper half of sram (if an eeprom is used). during this auto-load procedure the pentic+ will assert ireq low for rdy/bsy signaling, since the socket is configured at the memory-only interface during initialization. note that this auto-load operation occurs only after a hardware reset pulse. a software reset (including setting cor.sreset = 1) will not invoke this operation. eecs/fcs pulled high if eecs/ fcs is pulled high, this indicates that the configurations are stored in a flash memory. accordingly, after a power-on reset the pentic+ will automatically load the lan configuration registers from flash memory. the ethernet ids stored in the flash memory will be mapped into id registers automatically when they are read.
w89c926 pentic+ publication release date: january 1996 - 19 - revision a1 ce1,2 f/ee fcs msrd t > 20 ms sampling msd0-7 msan msan fcs msrd msd0-7 flash address t < 5 ms ireq reset t > 500 ns (rdy/bsy) t > 150 ns t > 60 ns t > 60 ns flash address t > 150 ns t > 150 s m s ce auto r fr foz fr foz eecs/fcs pulled low if eecs/ fcs is pulled low, this indicates that the configurations, ethernet id, and cis are stored in an eeprom. in this case, after a power-on reset the pentic+ will load the configurations into the lan configuration registers and the ethernet ids and cis into the higher half of sram memory (with auto-mapping to id registers and attribute memory space, respectively). since the eeprom used is a 93c66, a serial eeprom storage device, the access time is quite long and the system has to wait for the loading sequence (refer to pcmcia r2.1). loading a word of eeprom typically takes 34 m s. the exact time for eeprom loading depends on the length of cis but must not exceed 10 ms.
w89c926 pentic+ - 20 - reset ce1,2 f/ee eecs, rcs mswr t > 500 ns t > 20 ms t > 150 s sampling msd0-7 msan msan eecs msd0-2 msd0-7 rcs mswr 16 bit eeload low byte high byte even address odd address t < 10 ms ireq (rdy/bsy) t > 100 ns t > 100 ns t > 20 ns t > 20 ns t > 0.5 s t > 32 s m m m eer eeoz sw soz sw soz auto ce s r eeprom contents load back when an eeprom is used to store cis, the pentic+ allows the contents of the eeprom to be modified by means of the following sequence: write (eear, eos = 1 ew/er = 1) write (adr, address); write (adr, word_data); wait ( ); repeat ( read(eear, eos); ) until (eos = 0); /* the entire sequence should be consecutive or the process will be aborted. */
w89c926 pentic+ publication release date: january 1996 - 21 - revision a1 the adr register located at page3 04h of the core controller is used as a temporary register for eeprom read/write. when the eeprom load-back sequence specified above is performed, the content of the specified address will be overwritten by the new data. note that since the eeprom is word-aligned, each time the sequence is performed one word of data is modified. the address range available is from 00h to ffh. to make sure that the eeprom is written correctly, the programmer can use the following read-check process to read a word from a specified address in the eeprom. write (eear, eos = 1 ew/er = 0); write (adr, address); wait ( ); repeat ( read(eear, eos); ) until (eos = 0); read(adr); /* read word data */ /* the entire sequence should be consecutive or the process will be aborted. */ note that data will be kept in the adr until they are updated. that is, the data can be read out any time afterwards unless new data have been written. sram physical map when an eeprom is used for attribute memory storage, the 32k byte sram has two roles in the pentic+ design: the first 16k bytes of sram serve as an ethernet buffer ring, while the remainder is used for temporary storage of ethernet ids and cis storage (if eecs/ fcs is pulled low). the detailed physical mapping of the sram memory is shown in the table below. when a flash memory is used, only a 16k byte sram is needed to serve as the ethernet ring buffer. sram physical address eecs/ fcs pull low eecs/ fcs pull high 0000h- 3fffh ethernet buffer ethernet buffer 4000h id0 4001h id1 4002h id2 4003h id3 4004h id4 4005h id5 4006h board type (05h) 4007h checksum 4008h- 400dh - unused 400eh 57h 400fh 57h 4010h- 41fbh cis 41fch- 7fffh -
w89c926 pentic+ - 22 - note that if eecs/ fcs is pulled low, the cis is stored in the sram starting at address 4010h. the length of the cis depends on the word count specified in the first byte of eeprom. during a power- on reset, the pentic+ will load the exact word count specified in the eeprom rather than read in all bytes in the eeprom. the pentic+ will automatically translate the address from the host if the host tries to read cis. it will translate the attribute memory address by assuming that the first cis byte is stored at 00h of attribute memory, the second cis byte is stored at 02h, and so forth. users should assign cis accordingly, or else the cis may be lost. also note that for auto-load information write protection, the pentic+ will ignore any write operation above 4000h of sram. if it is necessary to change the settings, users should do so by writing the flash memory or eeprom. minimal system design a low-cost, dedicated lan card can be designed using the pentic+ chip, a 32k x 8 sram, a serial eeprom (93c66/93cs66), and a pig tail for the network interface mau, along with certain other peripheral components. the following is a sample cis table that can be used with this minimal system design: 01 03 dc 03 ff 17 03 5b 09 ff 1a 05 01 01 e0 1f 0f 1b 13 c1 c1 7d 19 55 15 26 00 33 43 16 45 70 ff ff 48 40 00 00 14 00 f0 09 'winicard' ff 21 02 06 03 20 04 u00 u01 u02 u03 15 14 04 01 u04 u05 u06 u07 u08 u09 u10 u11 u12 u13 u14 u15 u16 u17 u18 u19 00 ff ff ff flash memory access the flash access and the buffer sram share the same memory support bus. the address pins of the flash memory are directly connected to msa bus and data are accessed through the msd bus. eecs/ fcs is active low if it is pulled high and the attribute memory is accessed in the range 00000h to 03fffh or the common memory is accessed in the range 04000h to 1ffffh. note that cfb.fwe should be set to 1 before a flash write command is issued. i/o mode operation the i/o mode provides two dma channels for system access. the remote dma moves data between system memory space and local memory space. the local dma moves data between the fifo of the slct and local memory space. however, since the slct can handle local dma operations without system intervention (refer to the data sheet for the slct), the system has to perform only re- mote dma reads/writes. in a transmit operation, the data should first be moved from the system to local buffer memory. this is simply an "out" command on the pc. then the system orders the slct to start transmission, and the local dma starts to move data from buffer memory to the transmit fifo for transmission. in a receive operation, the local dma moves received data from the receive fifo to the buffer and asserts ireq to the system when the buffer rin g needs to be serviced. the system must move data
w89c926 pentic+ publication release date: january 1996 - 23 - revision a1 out before the buffer ring overflows. this is done through a remote dma read operation, which is simply a "in" command on the pc. shared memory mode operation in this mode, the local memory is mapped as part of the system memory. when it requires data transmission, the host fills the transmit buffer sram by a memory move operation and then issues a transmit command to the pentic+. when it receives data, the pentic+ will generate an interrupt to the host by a sserting ireq when one or more packets have been received. the pentic+ will then place the packets into the shared memory. the host should check the shared memory and remove the data before the buffer ring overflows. bus arbitration is performed between the host and lce core for shared memory usage. when memory accesses are issued, the arbiter will grant the bus master an acknowledge signal, which is a back to the lce or a wait signal to the host. there is no predefined priority in the pentic+; bus arbitration is performed on a first-come, first-served basis. to implement the shared memory mode, the pentic+ uses memory mapping register a (mma) and memory mapping register b (mmb) for memory mapping control. since the pentic+ will operate in 16-bit shared memory operation at shared memory base address 00000h only, 0s should be written to mmb and bit 0 to 5 of mma. the contents of the mma are described below. mma (memory mapping register a) mma is used for memory enable and software reset. it is located in i/o space, 00h, and can be ac- cessed only in shared memory mode. access address: iobase + 00h access type: write-only bit symbol description 0-5 - reserved. should be set to 0. 6 men if this bit is high, the buffer memory may be accessed by the system; if it is low, the buffer memory access is dis abled. this bit is 0 at power-on. 7 sreset a shared memory mode software reset is issued when a 1 is written to this bit. writing a 0 to this bit will clear the software reset. this bit is 0 at power-on. auto media-switching function the pentic+ also provides a user-friendly auto media-switching function. if the pentic+ is configured at the tpi, link checking is enabled, and the utp link is broken, the pentic+ will detect the link status and switch to the bnc port immediately. after the utp link is repaired, the pentic+ will detect the good link and switch back to the tpi again. if, however, the pentic+ is not configured at the tpi or link checking is disabled, the auto media- switching function will be disabled.
w89c926 pentic+ - 24 - bus arbitration and state diagram the pentic+ handles bus arbitration automatically. it can operate in four modes: idle state, slave read/write mode, dma mode, and shared memory mode. the pentic+ controls the on-board devices by decoding these modes. at power-on, the pentic+ is in idle mode. if a register read/write command is issued, the pentic+ enters the slave read/write mode. if a local dma or remote dma (i/o mode only) is initiated by the pentic+ core coprocessor, t he pentic+ enters dma mode. a memory command will place the pentic+ in memory mode. at any given time, the pentic+ can be in only one state. the pentic+ handles state changes automatically. however, two events, such as a dma command and a memory com mand, may be requested at the same time; in this case, the pentic+ allocates the bus on a first- come, first-served basis. no predefined priority is set within the pentic+. power-on reset idle slave read/ write dma operation memory operation register access core memory access access in cases where the system has no authority on the requested bus, the pentic+ will drive the wait pin low so that the system can insert wait states. after the pentic+ has released the bus authority, wait is deasserted to instruct the system to stop inserting wait states. slct core function the slct core coprocessor has five major logic blocks that control ethernet operations: the register files, transmit logic, receive logic, fifo logic, and dma logic. the relationship between these blocks is depicted in the following block diagram. pcmcia slot interface dma interface logic sna tx/rx logic 16-byte fifo transmit logic receive logic register file
w89c926 pentic+ publication release date: january 1996 - 25 - revision a1 core register files the register files of the slct can be accessed by means of io commands. the pentic+ should be in slave mode when the system accesses the register files. the command register (cr) determines the page number of the register file, while the system address ha<0:4> se lects one register address from 01h to 0fh (i/o mode) or from 10h to 1fh (shared memory mode). the pcmcia iord and iowr are the read/write commands used to activate the i/o opera tions. refer to the w89c90 data sheet for more detailed information on the registers. dma interface logic in i/o mapping mode, the slct provides two types of dma operations, local dma and remote dma. in shared memory mode, only local dma is available. local dma the local dma transfers data from/to the on-board buffers. to perform data reception or transmission from/to remote nodes in the network, data must be moved from/to the fifo. to enhance the effi- ciency of the transmission, the local dma transfers data in batches: data are first collected and then moved in a batch. up to 12 bytes of data can be moved in each transfer. this scheme reduces time wasted in requesting the bus. a local dma begins by requesting the local bus. if the local bus is available to the slct core, the bus arbiter inside the pentic+ responds at once by asserting the bus acknowledge (back, refer to lce); if, on the other hand, the bus is currently authorized to another device, the arbiter will not assert the bus acknowledge and the slct must wait. note that this sequence will not affect the host system or system bus signals. after each batch of data is transferred, the slct checks the fifo threshold levels to determine if another batch transfer should be requested. remote dma a remote dma can be performed only in i/o mode. the remote dma moves data between the host and the local buffers. unlike a local dma, the remote dma is word-wide: the remote dma operation transfers one word each time. since a remote dma is simply a system i/o operation, it sometimes affects the system bus. if the remote dma is interleaved with other devices, wait is asserted to force the system to insert wait states. the pentic+ will automatically handle any arbitration necessary.
w89c926 pentic+ - 26 - fifo logic the slct has a 16-byte fifo, which acts as an internal buffer to compensate for differences in the transmission/reception speed of different dmas. the fifo has fifo threshold pointers to determine the level at which it should initiate a l ocal dma. the threshold levels, which are different for reception and transmission, are defined in the dcr register. the fifo logic also provides fifo overrun and underrun signals for network management purposes. if received packets are flooding into the fifo but the slct still does not have bus authority, the fifo may be overrun. on the other hand, if a transmission begins before data are fed into the fifo, it may be underrun. either case results in a network error. fifo overruns and underruns can be prevented by changing the values of the fifo thresholds. normally, the data in the fifo cannot be read; reading fifo data during normal operation may cause wait to be asserted and the system to hang. in loopback mode, however, the slct allows fifo data to be read by byte in order to check the correctness of the loopback operation. receive logic the receive logic is responsible for receiving the serial network data and packing the data in byte/word sequence. the receive logic thus has serial-to- parallel logic in addition to network detection capability. the pentic+ accepts both physical addresses and group addresses (multicast and broadcast ad- dresses). the slct extracts the address field from the serial input data. it then determines if the address is acceptable according to the configurations defined in the receive configuration register (rcr). if the address is not acceptable, the packet reception is aborted. if the address is acceptable, the data packet is sent to the serial-to-parallel logic before being fed into the fifo. after receiving a data packet, the slct automatically adds four bytes of data receive status, next packet pointer, and two bytes of receive byte count into the fifo for network management purposes. the receive status contains the status of the incoming packet, so that the system can determine if the packet is desired. the next packet pointer points to the starting address of the next packet in the local receive ring. the receive byte count is the length of the packet receiv ed by the slct. note that the receive byte count may be different from the "length" field specified in the ethernet packet format. these four bytes of data will be transferred to the local buffer with the last batch of the local dma. however, these four bytes are stored at the first four addresses of the packet. transmit logic the slct must be filled before transmission may begin. that is, the local dma read must begin before the slct starts transmission. the slct first transmits 62 bits of preamble, then two bits of sfd, and then the data packet. the parallel-to-serial logic serializes the data from the fifo into a data packet. after the data packet, the slct optionally adds four bytes of cyclic redundancy code (crc) to the tail of the packet. a protocol pla determines the network operations of the pentic+. collision detection, random back- off, and auto retransmit are implemented in the transmit logic. the protocol pla ensures that the pentic+ follows the ieee 802.3 protocol. sna module the pentic+ also contains a serial network adaptor (sna), which adapts the non-return-to-zero (nrz) used in the core processor and host system to manchester coded network symbols. two kinds of in terfacing signals are provided in the pentic+: an aui interface for ethernet and a coaxial
w89c926 pentic+ publication release date: january 1996 - 27 - revision a1 interface for cheapernet. the sna contains three blocks: a phase locked loop (pll), a manchester en coder/decoder, and a collision decoder as well as crystal/oscillator logic. tp or coax aui interface pll osc/ crystal transmit logic receive logic l c e the manchester encoder/decoder handles code interpretation between nrz signals and manchester coded signals. the pll locks the receiving signals with an internal voltage control oscillator (vco) so that network noise can be eliminated before the signals enter the core coprocessor. the collision de- coder detects whether a collision has occurred on the network. the oscillator logic supplies the pentic+ with the required 20 mhz clock. this clock also supplies the sna clocking system. twisted pair interface module function transmit driver there are two signals for data transmission: the true and complement manchester differential data (txo+/-). these two signals are resistively combined to form a pre-equalized differential pair, which is then passed to the twisted-pair cable via a transmitter filter and an optional common mode choke. smart squelch the main function of this block is to determine when valid data are present on the differential receiving inputs (rxi+/-). to ensure that impulse noise on the medium will not be taken to be valid data, this circu it adopts a combination of amplitude and timing measurements to determine the validity of the input signals. to qualify incoming data, the smart squelch circuitry monitors the signals for three peaks of alternating polarity that occur within a 400 ns window. once this condition has been satis fied, the squelch level is reduced to minimize the noise effect and the chances of causing premature start of idle (soi) pulse detection. if the receiver detects activity on the receive line while packets are being transmitted, incoming data are qualified on five peaks of alternating polarity so as to prevent false collisions caused by impulse noise. the squelch function returns to its squelch state under any of the following conditions: a normal soi signal an inverted soi signal a missing soi signal a missing soi signal is assumed when no transitions have occurred on the receiver for 175 ns after a packet has arrived. in this case, a normal soi signal is generated and appended to the data.
w89c926 pentic+ - 28 - collision detection the collision detection logic determines when transmit and receive signals occur simultaneously on the twisted pair cable. collisions will not be reported when the device is in a link-fail state. the collision signal is also generated when the transceiver has detected a jabber condition or when the sqe test is being performed. sqe test the signal quality error (sqe) test is used to test the collision signaling circuitry in the twisted-pair transceiver module. after each packet transmission, an sqe signal is sent to the slct. the slct expects this signal and will flag an error if it does not exist. jabber the jabber timer monitors the transmitter and disables the transmission if the transmitter is active for greater than 26.2 ms. the jabber will re-enable the transmitter after the slct has been idle for at least 420 ms. link integrity during periods of inactivity, link pulses are generated and received by both maus at either end of the twisted pair to ensure that the cable has not been broken or shorted. a positive, 100 ns link integrity signal is generated by the twisted-pair transceiver and transmitted on the twisted pair cable every 13 ms during periods of no transmission activity. the pentic+ assumes a link-good state if it detects valid link pulse activity on the twisted-pair transceiver receive circuit. if neither receive data nor a link pulse (positive or negative) is detected within 105 ms, the pentic+ enters a link-fail state. when a link-fail condition occurs, four consecutive positive link pulses (or eight negative link pulses) must be received before a link-good condition is assumed. lce core registers this section lists the access addresses and access types of the lce core registers. refer to the w89c90 or w89c901 data sheet for more detailed information. page 0 address assignments (ps1 = 0, ps0 = 0) ra0-3 read write 00 command (cr) command (cr) 01 current local dma address 0 (clda0) page start register (pstart) 02 current local dma address 1 (clda1) page stop register (pstop) 03 boundary pointer (bnry) boundary pointer (bnry) 04 transmit status register (tsr) transmit page start address (tpsr) 05 number of collisions register (ncr) transmit byte count register 0 (tbcr0) 06 fifo (fifo) transmit byte count register 1 (tbcr1) 07 interrupt status register (isr) interrupt status register (isr) 08 current remote dma address 0 (crda0) remote start address register 0 (rsar0)
w89c926 pentic+ publication release date: january 1996 - 29 - revision a1 page 0 address assignments (ps1 = 0, ps0 = 0), continued ra0-3 read write 09 current remote dma address 1 (crda1) remote start address register 1 (rsar1) 0a reserved remote byte count register 0 (rbcr0) 0b reserved remote byte count register 1 (rbcr1) 0c received status register (rsr) receive configuration register (rcr) 0d tally counter 0 (frame alignment errors) (cntr0) transmit configuration register (tcr) 0e tally counter 1 (crc errors)(cntr1) data configuration register (dcr) 0f tally counter 2 (missed packet errors) (cnrt2) interrupt mask register (imr) page 1 address assignments (ps1 = 0, ps0 = 1) ra0-3 read write 00 command (cr) command (cr) 01 physical address register 0 (par 0) physical address register 0 (par 0) 02 physical address register 1 (par 1) physical address register 1 (par 1) 03 physical address register 2 (par 2) physical address register 2 (par 2) 04 physical address register 3 (par 3) physical address register 3 (par 3) 05 physical address register 4 (par 4) physical address register 4 (par 4) 06 physical address register 5 (par 5) physical address register 5 (par 5) 07 current page register (curr) current page register (curr) 08 multicast address 0 (mar 0) multicast address 1 (mar 0) 09 multicast address 1 (mar 1) multicast address 1 (mar 1) 0a multicast address 2 (mar 2) multicast address 2 (mar 2) 0b multicast address 3 (mar 3) multicast address 3 (mar 3) 0c multicast address 4 (mar 4) multicast address 4 (mar 4) 0d multicast address 5 (mar 5) multicast address 5 (mar 5) 0e multicast address 6 (mar 6) multicast address 6 (mar 6) 0f multicast address 7 (mar 7) multicast address 7 (mar 7)
w89c926 pentic+ - 30 - page 2 address assignments (ps1 = 1, ps0 = 0) ra0-3 read write 00 command (cr) command (cr) 01 page start register (pstart) current local dma address 0 (clda0) 02 page stop register (pstop) current local dma address 1 (clda1) 03 remote next packet pointer remote next package pointer 04 transmit page start address (tpsr) reserved 05 local next packet pointer local next packet pointer 06 address counter (upper) address counter (upper) 07 address counter (lower) address counter (lower) 08 reserved reserved 09 reserved reserved 0a reserved reserved 0b reserved reserved 0c receive configuration register (rcr) reserved 0d transmit configuration register (tcr) transmit configuration 0e data configuration register (dcr) reserved 0f interrupt mask register (imr) reserved note: page 2 registers should be accessed only for diagnostic purposes. they should not be modified during operation. page 3 should never be modified. electrical specifications absolute maximum ratings parameter symbol min. max. unit operating temperature t a 0 70 c storage temperature t s -55 150 c supply voltage v dd -0.5 7.0 v input voltage v in v ss -0.5 v dd +0.5 v output voltage v out v ss -0.5 v dd +0.5 v lead temperature (soldering 10 seconds maximum) t l - 250 c esd tolerance esd 2k - v note: exposure to conditions beyond those listed under absolute maximum ratings may adversely affect the life and reliability of the device.
w89c926 pentic+ publication release date: january 1996 - 31 - revision a1 dc characteristics power supply: (v dd = 4.75v to 5.25v, v ss = 0v, t a = 0 c to 70 c) parameter sym. conditions min. max. unit average idle supply current note 1 i avi v dd = 5.25v - 150 ma average transmit supply current note 2 i avt v dd = 5.25v - 250 ma notes: 1. x1 = 20 mhz, v in = v cc or gnd. 2. x1 = 20 mhz, normal transmitting operation. digital: (v dd = 4.75v to 5.25v, v ss = 0v, t a = 0 c to 70 c) parameter sym. conditions min. max. unit low input voltage v il v ss -0.5 0.8 v high input voltage v ih 2.0 v dd +0.5 v low output voltage v ol v dd = 4.75v, i ol = i ol - min - 0.4 v high output voltage v oh v dd = 4.75v, i oh = i ol - max 2.4 - v low output sink current i ol1 4 ma high output drive current i oh1 - -4 ma low output sink current* i ol2 2 - ma high output drive current* ioh2 - -2 ma output 3-state leakage current iotr v dd = 5.25v - 10 m a * these are the parameteres for msd0-7 and msa0-15. aui: (v dd = 4.75v to 5.25v, v ss = 0v, t a = 0 c to 70 c) parameter sym. conditions min. max. unit differential output voltage (tx+/- ) v dd with test load +/-550 +/-1200 mv differential output voltage imbalance (tx+/-) v ob with test load - 40 mv undershoot voltage (tx+/-) v u with test load - 100 mv differential squelch threshold (cd+/-, rx+/-) v ds -175 -300 mv differential input common mode volt a ge (cd+/-, rx+/-) v cm 2.0 4.0 v
w89c926 pentic+ - 32 - twisted pair: (v dd = 4.75v to 5.25v, v ss = 0v, t a = 0 c to 70 c) parameter sym. conditions min. max. unit rxi+/- differential input resistance r ti 3 - k w rxi+/- open circuit input voltage (bias) v tib -2.75 v dd -1.0 v rxi+/- differential input voltage range v tiv v dd = 5v -3.1 3.1 v rxi+/- positive squelched threshold v tps 300 585 mv rxi+/- negative squelched threshold v tns -585 -300 mv rxi+/- positive unsquelched threshold v tpu 200 350 mv rxi+/- negative unsquelched threshold v tnu -350 -200 mv txo+/- differential output voltage v to with test load 2.2 2.8 v switching characteristics memory support bus access (sram access) msan t1 even address msdn (read) rcs msrd odd address valid valid t3 mswr valid msdn (write) valid t4 t12 t13 t7 t15 t2 t8 t11 t10 t6 t14 t5 t9 t16
w89c926 pentic+ publication release date: january 1996 - 33 - revision a1 sram (upper and lower values are for 70 ns and 15 ns srams, respectively) symbol description min. max. unit t1 read cycle time. 70 15 - - ns t2 msa0-15 valid to msd0-7 read data valid. - - 70 15 ns t3 msd0-7 read data hold valid from msa0-15 change. 5 3 - - ns t4 msd0-7 read data hold from msrd deasserted. 0 0 - - ns t5 rcs held valid after msrd deasserted. 5 3 - - ns t6 msa0-15 held valid after msrd deasserted. 5 3 - - ns t7 rcs asserted to mswr asserted 0 0 - - ns t8 mswr pulse width 60 15 - - ns t9 rcs asserted to mswr deasserted. 60 15 - - ns t10 msa0-15 held valid after mswr deasserted. 5 3 - - ns t11 msd0-7 write data setup before mswr asserted. 35 10 - - ns t12 msd0-7 write data hold after mswr deasserted. 5 3 - - ns t13 even byte mswr deasserted to odd byte mswr asserted. (see note) 10 5 - - ns t14 rcs held valid after mswr deasserted. 5 3 - - ns t15 even byte address invalid to odd byte address valid. (see note) 0 0 - - ns t16 command recovery time. 30 10 - - ns note: this timing is invalid for byte access, e.g, attribute memory reading on sram image.
w89c926 pentic+ - 34 - flash memory memory support bus access (flash access) t9 msan t1 t2 t3 t4 valid t7 t8 t6 t5 msdn (read) msdn (write) valid fcs msrd mswr t10 t11 t12 symbol description min. max. unit t1 msa0-16 valid to fcs asserted. 0 - ns t2 fcs asserted to msrd , mswr asserted. 20 - ns t3 msa0-16 held valid after msrd , mswr deasserted. 5 - ns t4a fcs held valid after msrd deasserted. 0 - ns t4b fcs held valid after mswr deasserted. 5 - ns t5 msrd asserted to read data valid. - 60 ns t6 read data hold from msrd deasserted. 0 - ns t7 write data setup to mswr deasserted. 55 - ns t8 write data hold from mswr deasserted. 15 - ns t9 access cycle time 150 - ns t10 write pulse width 55 ns t11 fcs asserted to mswr deasserted 75 - ns t12a write recovery time before read 6 - m s t12b read recovery time before write 0 - m s t12c consecutive same commands interval 20 - ns
w89c926 pentic+ publication release date: january 1996 - 35 - revision a1 attribute memory access ha0-16 ce1,2 oe we wait hd0-7 hd0-7 (write) (read) t6 t5 t7 valid t4 t8 valid t3 t1 t2 t11 t10 t18 reg low reg t12 t13 t14 t17 t9 t19 (even) (even) t15 t16 symbol description min. max. unit t1 ha0-16, reg valid to oe , we asserted 30 - ns t2 ce 1 , 2 asserted to oe , we asserted 0 - ns t3 oe , we asserted to wait asserted - 35 ns t4 oe asserted to hd0-7 read data valid (see note) - 150 ns t5 hd0-7 write data setup before we deasserted 80 - ns t6 hd0-7 write data hold from we deasserted 30 - ns t7 hd0-7 read data disable from oe deasserted - 100 ns t8 read data setup before wait deasserted 0 - ns t9 wait deasserted to oe , we deasserted 0 - ns t10 ce 1 , 2 hold valid from oe , we deasserted 20 - ns t11 ha0-16, reg hold valid from oe , we deasserted 20 - ns t12 ha0-16, reg setup to we deasserted 180 - ns
w89c926 pentic+ - 36 - attribute memory access, continued symbol description min. max. unit t13 ce 1 , 2 asserted to we deasserted 180 - ns t14 we pulse width 150 - ns t15 ha0-16, reg valid to read data valid (see note) - 300 ns t16 ce 1 , 2 asserted to read data valid (see note) - 300 ns t17 wait pulse width - 12 m s t18a oe deasserted to next we asserted 10 - ns t18b we deasserted to next oe asserted 10 - ns t19a read cycle time 300 - ns t19b write cycle time 250 - ns note: these timings are specified when the pentic+ does not assert wait . common memory access ha0-16 ce1,2 oe we wait hd0-15 hd0-15 (write) (read) t5 t4 t6 valid t7 valid t3 t1 t10 t9 t15 reg high reg t11 t12 t13 t14 t8 t16 t3
w89c926 pentic+ publication release date: january 1996 - 37 - revision a1 common memory access, continued symbol description min. max. unit t1 ha0-16, reg valid to oe , we assert. 20 - ns t2 ce 1 , 2 assert to oe , we assert. 0 - ns t3 oe , we assert to wait asserts. - 35 ns t4 hd0-15 write data setup before we deasserts. 50 - ns t5 hd0-15 write data hold from we deasserts. 20 - ns t6 hd0-15 read data disable from oe deasserts. - 75 ns t7 read data setup before wait deasserts. 0 - ns t8 wait deasserts to oe , we deassert. 0 - ns t9 ce 1 , 2 hold valid from oe , we deassert 20 - ns t10 ha0-16, reg hold valid from oe , we deassert 20 - ns t11 ha0-16, reg setup to we deassert 100 - ns t12 ce 1 , 2 assert to we deassert 100 - ns t13 we pulse width 80 - ns t14 wait pulse width - 12 m s t15a oe deassert to next we assert 10 - ns t15b we deassert to next oe assert 10 - ns t16a read cycle time 150 - ns t16b write cycle time 150 - ns
w89c926 pentic+ - 38 - pcmcia bus slave access t15 t14 han t1 t2 t3 t4 t7 t17 t16 t28 t10 t18 t9 t5 t6 hdn (read) hdn (write) msan t20 t11 t13 even address t23 t21 msdn (read) reg ce oe we , iord iowr , iois16 wait inpack rcs msrd mswr odd address msdn (write) t25 t26 t22 t24 t27 t8 t12 t19
w89c926 pentic+ publication release date: january 1996 - 39 - revision a1 pcmcia bus slave access symbol description min. max. unit t1a ha0-16 & reg valid to oe , we asserted note 2 10 - ns t1b ha0-16 & reg valid to iord , iowr asserted. note 3 5 - ns t2a ce 1 , 2 asserted to oe , we asserted. 0 - ns t2b ce 1 , 2 asserted to iord , iowr asserted. 5 - ns t3a ha0-16 valid to oe , we asserted. 10 - ns t3b ha0-16 valid to iord , iowr asserted. 70 - ns t4 ha0-16 valid to iois 16 asserted. note 4 - 35 ns t5 oe , we , iord , iowr asserted to wait asserted. note 1 - 35 ns t6 iord asserted to inpack asserted. note 8 - 40 ns t7a iord asserted to hd0-15 read data valid. note 6 - 100 ns t7b oe asserted to hd0-15 read data valid. note 9 - 50 ns t8 iord , iowr minimum width time. 165 - ns t9a wait deasserted to hd0-15 memory read data valid. note 1, 5 - 0 ns t9b wait deasserted to hd0-15 i/o read data valid. note 1, 5 - 0 ns t10 hd0-15 read data hold after oe , iord deasserted. 5 - ns t11 hd0-15 write data setup before we deasserted. 40 - ns t12 hd0-15 write data setup befor iowr assert. 60 - t13a hd0-15 write data hold after we deasserted. 15 - ns t13b hd0-15 write data hold after iowr deasserted. 30 - ns t14a oe , we deasserted to reg deasserted. note 7 15 - ns t14b iord , iowr deasserted to reg deasserted. note 7 0 - ns t15a oe , we deasserted to ce 1 , 2 deasserted. 15 - ns t15b iord , iowr deasserted to ce 1 , 2 deasserted. 20 - ns t16a oe , we deasserted to ha0-16 deasserted. 15 - ns
w89c926 pentic+ - 40 - pcmcia bus slave access, continued symbol description min. max. unit t16b iord , iowr deasserted to ha0-16 deasserted. 20 - ns t17 ha0-16 deasserted to iois 16 deasserted. note 4 - 30 ns t18 iord deasserted to inpack deasserted. - 40 ns t19 msa0-14 asserted t0 wait deasserted. note 1 - 265 ns t20 ce 1 , 2 asserted to rcs asserted. - 265 ns t21 oe , asserted to roe asserted. note 2 - 215 ns t22 msd odd byte read data valid to hd0-15 read data valid. - 35 ns t23a msd odd byte read data hold after msrd deasserted. 5 - ns t23b msd odd byte read data hold after msrd deasserted. note.10 3 - ns t24 msa0-14 valid to mswr asserted. 0 - ns t25 second mswr asserted before wait deasserted. note 1 - 140 ns t26a msd write data setup before mswr deasserted. 35 - ns t26b msd write data setup before mswr deasserted. note.10 10 - ns t27a msd write data hold after mswr deasserted. 5 - ns t27b msd write data hold after mswr deasserted. note.10 3 - ns t28 command deasserted to next command asserted 150 - ns notes: 1. this is the timing for insert wait states. wait is asserted if the core cannot service the access immediately; it will hold asserted until the core is ready, causing the system to insert wait states. 2. this is the timing for shared memory access. 3. this is the timing for i/o access. 4. iois 16 is asserted for 16-bit i/o transfers. 5. read data valid is referenced to wait when wait states are inserted. 6. if no wait states are inserted, read data valid can be referenced from oe , iord . 7. reg is asserted for i/o access and it is deasserted for common memory access. 8. inpack is asserted only for i/o read operation. 9. this is a shared memory access without bus contention. 10. this is the timing for sram-15.
w89c926 pentic+ publication release date: january 1996 - 41 - revision a1 h/w reset and auto-initialization timing cen reset ireq eecs/fcs sampling eecs/fcs msrd mswr eecs/fcs floating auto-loading msd0-7 msan flash memory loading flash auto-loading (if eecs/fcs pulled high) serial eeprom loading sram write eeprom auto-loading (if eecs/fcs pulled low) sram write even byte odd byte t4 t7 t6 t6 t5 t5 t1 t3 t2 flash memory loading symbol description min. max. unit t1 reset pulse width 500 - ns t2 reset deasserted to eecs/ fcs sampling 400 - ns t3 reset deasserted to ce 1 , 2 asserted 20 - ms t4 nonvolatile memory auto-load time - 10 ms t5 flash memory auto-reading recovery time 60 - ns t6 sram image auto-writing recovery time 20 - ns t7 eeprom auto-reading recovery time 50 - ns
w89c926 pentic+ - 42 - serial eeprom timing t2 t1 t5 t6 t8 t3 t7 t4 eecs msd2 (sck) msd1 (di) msd0 (do) serial eeprom timing symbol description min. max. unit t1 eecs asserted to sk 500 ns t2 eecs hold from sk 0 - ns t3 msd2 off time 500 - ns t4 msd2 on time 500 - ns t5 msd2 clock period 1 - m s t6 msd1 set up time to msd2 high 500 - ns t7 msd1 hold time from msd2 high 500 - ns t8 msd0 valid from msd2 high 500 ns aui transmit timing (end of transmit) t 0 1 0 tx+/- tx+/- 1 0 1 toi t toh
w89c926 pentic+ publication release date: january 1996 - 43 - revision a1 symbol description min. max. unit t toh transmit output high before idle 200 ns t toi transmit output idle time 8000 ns aui receive timing (end of receive) 1 1 rx+/rxi+ rx-/rxi- rx+/rxi+ 0 0 rx-/rxi- t eop0 t eop1 symbol description min. max. unit t eop1 end of packet received hold time after logic "1" 200 ns t eop0 end of packet received hold time after logic "0" 200 ns note: these parameters are specified by design and are not tested. link pulse timing txo+ txo- t lpw t lpi symbol description min. max. unit t lpi link output pulse interval 8 24 ms t lpw link output pulse width 80 120 ns
w89c926 pentic+ - 44 - tpi transmit timing (end of transmit) 0 1 1 txo+ txo- txo+ txo- t eth1 t eth1 symbol description min. max. unit t eth1 end of packet transmitted hold time 1 (txp/n) 250 ns note: this parameter is specified by design and is not tested. ac timing test conditions parameter test conditions supply voltage (v dd /v ss ) 5v 0.25v temperature 25 c/70 c input test pattern levels (ttl/cmos) gnd to 3.0v input rise and fall times (ttl/cmos) 5 ns input and output pattern reference level (ttl/cmos) 1.3v input waveform level (diff) -350 to -1315 mv input and output waveform reference levels (diff) 50% point of the differential 3-state reference levels float (v) 0.5v note: the above specifications are valid only if the mandatory isolations are properly employed and all dif ferential signals are taken to the aui of the pulse transformer.
w89c926 pentic+ publication release date: january 1996 - 45 - revision a1 output load 0.1 f device vcc rl = 2.2k sw1 (note 3) output cl (note 1, 2) under input test m notes: 1. load capacitance employed depends on output type: for 3sl, mos, tpi, aui: cl = 50 pf for 3sh, och: cl = 240 pf 2. specifications which measure delays from an active state to a high-z state are not guaranteed by production testing, but are characterized using 240 pf and are correlated to determine true driver turn-off time by eliminating inherent r-c delay times in measurements. 3. sw1 = open for push-pull outputs during timing test. sw1 = v cc for v ol test. sw1 = gnd for v oh test. sw1 = v cc for high-z to active low and active low to high-z measurements. sw1 = gnd for high-z to active high and active high to high-z measurements. pin capacitance t a = 25 c, f = 1 mhz symbol parameter typ unit c in input capacitance 7 pf c out output capacitance 10 pf derating factor output timing is measured with a purely capacitive load of 50 pf or 240 pf. the following correction factor can be used for other loads (this factor is preliminary): derating for 3sl, mos = -0.05 ns/pf derating for 3sh, ocl, tpi = -0.03 ns/pf
w89c926 pentic+ - 46 - aui transmit test load r = 78 tx+ tx- m 27 h note: in the above diagram, the tx+ and tx- signals are taken from the aui side of the pulse transformer. the pulse transformer used for all testing is a 100 m h +/-0.1% pulse engineering pe64103. utp transmit test load r = 100 1% txo+ txo- utp filter r = 1.21k 1% note: in the above diagram, the utp filter used for all testing is a valor fl1012.
w89c926 pentic+ publication release date: january 1996 - 47 - revision a1 package dimensions the pentic+ is packaged in a 100-pin tqfp for type ii pc card applications. detailed dimensions are shown below. he e hd d e b w89c926f @ c l1 l a2 a1 d y symbol a1 a2 b c d e e hd he l l1 y @ dimensions in inches dimensions in mm 0 to 7 0.10 +/- 0.05 1.40 +/- 0.05 0.32 + 0.06 0.20 max 14.00 + 0.10 20.00 + 0.10 0.65 typ 16.00 + 0.10 22.00 + 0.10 0.60 + 0.15 1.00 typ 0.08 max 0 to 7 - 0.10 0.09 min 0.004 +/- 0.002 0.055 +/- 0.002 0.013 + 0.002 - 0.004 0.008 max 0.004 min 0.551 + 0.004 0.787 + 0.004 0.026 typ 0.630 + 0.004 0.866 + 0.004 0.024 + 0.006 0.039 typ 0.003 max - - - - - - - - - -
w89c926 pentic+ - 48 - headquarters no. 4, creation rd. iii, science-based industrial park, hsinchu, taiwan tel: 886-3-5770066 fax: 886-3-5792668 http://www.winbond.com.tw/ voice & fax-on-demand: 886-2-7197006 taipei office 11f, no. 115, sec. 3, min-sheng east rd., taipei, taiwan tel: 886-2-7190505 fax: 886-2-7197502 winbond electronics (h.k.) ltd. rm. 803, world trade square, tower ii, 123 hoi bun rd., kwun tong, kowloon, hong kong tel: 852-27513100 fax: 852-27552064 winbond electronics north america corp. winbond memory lab. winbond microelectronics corp. winbond systems lab. 2727 n. first street, san jose, ca 95134, u.s.a. tel: 1-408-9436666 fax: 1-408-5441798 note: all data and specifications are subject to change without notice.

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